power supply circuit, et type power amplifier and eer type power amplifier

专利摘要:
ENERGY SUPPLY CIRCUIT. Problem: To provide a power supply circuit that is used in a transmitter that performs wireless broadband communication, which increases the conversion efficiency of the power supply, and with which it is possible to minimize the changeover transition time. voltage level, as well as improving the distortion characteristics of the output signals. Solution: A power supply circuit includes: a Push-pull amplifier unit that amplifies an input signal with a ush-pull amplification protocol; a variable power supply unit, which varies, with a control signal, the voltage level of a power supply voltage that is supplied to the Push-pull amplifier; a switching control unit (83 ') which, based on the input signal, emits the control signal that controls the voltage level of the current supply voltage; and a timing control unit (121) that applies a specific time delay to the input signal. When the control signal rises, the switching control unit (83 ') causes the control signal to rise for a longer time delay (...).
公开号:BR112014012553B1
申请号:R112014012553-8
申请日:2012-11-19
公开日:2020-12-29
发明作者:Toshiyuki Nagasaku；Manabu Nakamura；Taizo Ito
申请人:Hitachi Kokusai Electric Inc.；
IPC主号:

专利说明:

DESCRIPTION TECHNICAL FIELD
[0001] The present invention relates to a power supply circuit for use in power amplifiers of transmitters that carry out radio communication by means of high frequency broadband signals, and more particularly to a power supply circuit capable of to improve energy conversion efficiency. PREVIOUS ART Explanation of Prior Art
[0002] As a demand for transmitter power amplifiers, size reduction and weight reduction are strongly required due to the restriction of installation locations, for the purpose of reducing installation costs. Although the majority of the volume / weight of equipment is occupied by a module with radiation fins, which is for the release of heat to be generated by the loss of electrical energy, it is possible, by improving energy efficiency, to make the fin less radiation, which contributes to the reduction in size and weight. [Power Amplifier for Improving Energy Efficiency: Figure 12]
[0003] The methodology for improving energy efficiency includes the ET (Envelope Tracking) scheme to control a current supply voltage to be applied to a power amplifier in accordance with the voltage amplitude of a signal fed to the power amplifier. , and the EER (Envelope Elimination and Restoration) scheme to vary a supply voltage for a saturation type power amplifier.
[0004] Power amplifiers employing ET and EER schemes will be explained with reference to figure 12. Figure 12 (a) is a diagram showing schematically a configuration of an ET type power amplifier, and (b) is a diagram schematic configuration of an EER power amplifier. [ET Power Amplifier: Figure 12 (a)]
[0005] As shown in figure 12 (a), the ET power amplifier includes an input terminal 1, divider 2, envelope wave detector 3, power supply circuit 4, main amplifier 6, and output terminal 7.
[0006] More specifically, the input terminal 1, divider 2, main amplifier 6 and output terminal 7 are connected in series. Connected to divider 2 is the envelope wave detector 3; connected to the envelope wave detector 3 is the power supply circuit 4. The power supply circuit 4 is connected to the main amplifier 6, providing a configuration for supplying electrical power.
[0007] In the ET scheme, an RF signal fed from the input terminal 1 is distributed through the divider 2: one is fed to the envelope wave detector 3 to extract an envelope curve and to feed it into the supply circuit power supply circuit 4. The power supply circuit 4 varies a supply voltage being applied to the main amplifier 6 by a voltage that is equal to, or slightly greater than, the envelope at the output of the main amplifier 6.
[0008] Consequently, a difference between the supply voltage applied to the main amplifier 6 and the output signal amplitude is suppressed to a lower level, thus allowing the main amplifier 6 to operate in a region that is lower in power loss. .
[0009] EER power amplifier: figure 12 (b)
[0010] As shown in figure 12 (b), the EER power amplifier has an input terminal 1, divider 2, envelope wave detector 3, power supply circuit 4, RF limiting amplifier 5, main amplifier 6 and output terminal 7.
[0011] Briefly, this is different from the ET power amplifier, in that the RF limiting amplifier 5 is provided between divider 2 and main amplifier 6 to limit an input voltage applied to the main amplifier 6.
[0012] In the EER power amplifier with the above mentioned configuration, the RF signal fed from the input terminal 1 is distributed by the divider 2: one is detected by the envelope wave detector 3, resulting in a signal of envelope being fed to the power supply circuit 4. Then, the power supply circuit 4 varies a supply voltage of the main amplifier 6 according to the envelope signal.
[0013] The other RF signal distributed by the splitter 2 is subject to the removal of amplitude fluctuation components in the RF limiting amplifier 5 and then amplified by the main amplifier 6, while retaining only phase information.
[0014] As a current supply voltage from the main amplifier 6 varies according to the amplitude information from the envelope wave detector 3, the amplitude information is re-stored, allowing the main amplifier 6 to always operate at its state of saturation; thus, high efficiency is achieved.
[0015] Quickly Operable Power Supply Circuit: Figure 13
[0016] Incidentally, when considering the efficiency of a total ET / EER power amplifier, not only the efficiency of the main amplifier 6, but also the efficiency of the power supply circuit 4 becomes important.
[0017] Broadband signal envelope signals, such as a W-CDMA signal (Access by Multiple Division by Broadband Code) and an OFDM signal (Orthogonal Frequency Division Multiplexing), are wide in the band; thus, the current supply circuit 4 is required to operate at high speeds.
[0018] Examples of such a power supply circuit, capable of operating quickly, are set out in Non-Patent Literature 1 and Non-Patent Literature 2 (see Non-Patent Literature 1, 2).
[0019] Power supplies that can be operated quickly include one that uses a Push-pull amplifier as the linear amplifier circuit and uses a class D circuit as the DC / DC converter.
[0020] An example of configuring such a power supply circuit will be explained using figure 13. Figure 13 is a configuration diagram showing an example of a power supply circuit, which can be quickly operated.
[0021] As shown in figure 13, the power supply circuit, operable quickly (power supply circuit operating at high speed) is generally constituted by an input terminal 8, a Push-pull amplifier 12 which is a source broadband voltage, a combination of current detector 25 and hysteresis comparator 26 that serve as a control circuit, a high efficiency DC / DC converter 11, and an output terminal 9.
[0022] Note that the Push-pull amplifier 12 corresponds to the Push-pull amplifier unit defined in the attached claims.
[0023] And, the input terminal 8 is connected to an output stage of the envelope wave detector 3, shown in figure 12; the output terminal 9 is connected to a power supply terminal of the main amplifier 6, shown in figure 12.
[0024] Current detector 25 is made up of a resistor, for example.
[0025] Note that the DC / DC converter 11 has a voltage source, switching element 13, diode 14 and inductance 15.
[0026] Regarding the Push-pull 12 amplifier, this will be described later.
[0027] DC / DC Converter Operation 11
[0028] An operation of the DC / DC converter 11 will be explained shortly.
[0029] In a case in which an output of the envelope wave detector 3 is a DC component, the DC / DC converter 11 operates in a tracking mode and causes switching element 13 to periodically switch on and off at a frequency of self-excitation.
[0030] When the output of the envelope wave detector 3 becomes the DC component and the high frequency AC component, the DC / DC converter 11 operates in a non-tracking mode, to cause the element switch 13 turns on and off at a frequency basically equal to the high frequency AC component. At this time, the DC / DC converter 11 emits the DC component only while causing the high frequency AC component to be supplied from the Push-pull amplifier 12.
[0031] Energy Supply Circuit Efficiency
[0032] In the high speed operating power supply circuit, shown in figure 13, it is conceivable to try to improve the efficiency of the power supply circuit by increasing the frequency of self-excitation to thereby increase a traceable AC component, that is, by increasing the energy ratio provided from a high efficiency DC / DC converter 11.
[0033] However, in broadband communication systems, such as WiMAX (Worldwide Interoperability for Microwave Access) and LTE (Long Term Evolution) and similar, the envelope also becomes wider in the band; thus, an increase in switching frequency of the DC / DC converter 11 also results in an increase in switching loss, which leads to a reduction in efficiency of the current supply circuit.
[0034] In view of this, appropriate circuit constants are prepared to arrange broadband communication systems, such as WiMAX, LTE and others, in such a way as to supply low frequency AC components from DC converter / High-efficiency DC 11, while providing high-frequency AC components from the Push-pull amplifier 12.
[0035] Dealing with Large Power Supply Circuit Current
[0036] By the way, in cases where the output energy of the main amplifier 6 is significant, it is also necessary to supply a large amount of current from the current supply circuit 4.
[0037] In the high speed operating power supply circuit of figure 13, those components capable of letting the required current flow can be selected for use as switching element 13, diode 14 and inductance 15 in the DC / DC converter 11 .
[0038] However, in relation to an operational amplifier used for the Push-pull amplifier 12, there are, in general, no components capable of letting such large currents flow through them. Consequently, NPN and PNP transistors are connected to an output of the operational amplifier, thus increasing the capacity of the current that can be supplied.
[0039] Push-pull amplifier configuration: figure 13
[0040] Next, a configuration of the Push-pull amplifier (previously known Push-pull amplifier) for use in the traditional high speed operating power supply circuit will be explained using figure 13.
[0041] As shown in figure 13, the traditional Push-pull amplifier 12 is configured from an operational amplifier 16, a polarization circuit consisting of resistor 19, diode 20, diode 21 and resistor 22, a push-pull circuit constituted from the transistor NPN 17 and the transistor PNP 18, DC voltage source 23, and DC voltage source 24.
[0042] And, in the Push-pull amplifier 12 with this configuration, an input signal is fed through input terminal 8 to the “+” terminal of the operational amplifier 16; an output signal is fed back to the “-” terminal of this operational amplifier.
[0043] Diode 20 is to compensate for a voltage drop between the base and emitter of the transistor NPN 17; diode 21 is to compensate for a voltage drop between the base and emitter of the PNP transistor 18. These diodes constitute the polarization circuit together with resistor 19 and resistor 22.
[0044] The NPN transistor 17, which is connected to the DC voltage source 23 which is set to a higher voltage value than the DC voltage source 24, and the PNP transistor 18, which is connected to the voltage source DC 24 being set to a lower voltage value than DC 23 voltage source, perform amplification by push-pull operations.
[0045] Then, the NPN 17 transistor emits a higher voltage than a reference voltage; the PNP 18 transistor emits a lower voltage than the reference voltage.
[0046] Output waveforms from the NPN 17 transistor and PNP 18 transistor become semi-rectified waveforms of a sine wave: this corresponds to a class B polarized amplifier. An output waveform from the Push amplifier -pull 12 becomes a composite of the output waveform of transistor NPN 17 and the output waveform of transistor PNP 18.
[0047] The Energy Conversion efficiency of the Class B Amplifier: figure 14
[0048] Here, an explanation will be given of the energy conversion efficiency of the Class B amplifier.
[0049] As is well known, the energy conversion efficiency n when the class B amplifier emits a sine wave is represented by Equation 1. n = π / 4 x Vomax / Vdd. (Eq. 1)
[0050] Explaining Equation 1 for transistor NPN 17, Vdd is a current supply voltage of the DC voltage source 23, and Vomax is the maximum value of an output voltage of transistor NPN 17.
[0051] In Equation 1, the energy conversion efficiency n is 78.5% in the case of Vomax being the same voltage as Vdd - that is, in the case of a saturation output. When the maximum Vomax output voltage decreases, the energy conversion efficiency n also decreases.
[0052] Figure 14 is an explanatory diagram showing the power conversion efficiency characteristics of the Class B amplifier.
[0053] Figure 14 shows the energy conversion efficiency n for the output voltage, in which the lateral axis power reduction is one that represents Vomax / Vdd logarithmically.
[0054] A point at which the power reduction is 0 dB indicates the saturation output. The energy conversion efficiency n at this point is 78.5 %%, as previously mentioned. When the power reduction becomes greater (when the maximum Vomax output voltage decreases), the energy conversion efficiency n decreases. When the power reduction is -8dB, the energy conversion efficiency n becomes 30%.
[0055] The energy conversion efficiency of the Push-pull Amplifier: figure 14
[0056] Although in Equation 1 and figure 14 an explanation has been given with respect to the transistor NPN 17, the same is also true for the transistor PNP 18; thus, the characteristics of an entire Push-pull amplifier 12 can also be represented by Equation 1 and figure 14.
[0057] Note here that, although in the Push-pull amplifier 12 the operational amplifier 16 and polarization circuit also consume energy, the energy conversion efficiency of the Push-pull amplifier 12 is almost identical to the characteristics shown in figure 14, because the current amplification factors hfe of the NPN transistor 17 and the PNP transistor 18 are large and the power consumption of the operational amplifier 16 is small compared to that of the Push-pull amplifier 12.
[0058] Example of Cumulative Probability Density Distribution of the Envelope Signal Spectrum in the OFDM signal: figure 15
[0059] An explanation will be given here, using figure 15, of the cumulative probability density distribution of an envelope signal in the OFDM signal. Figure 15 is an explanatory diagram showing an example of the cumulative probability density distribution of the envelope signal in the OFDM signal.
[0060] In figure 15, an OFDM modulation signal envelope curve with a bandwidth of 10 MHz and PAPR (Peak to Average Power Ratio) of 8 dB was obtained; then, the cumulative probability density distribution of electricity was plotted from DC to 10 MHz.
[0061] As mentioned above, although the current supply circuit 4 provides DC and low frequency components from the DC / DC converter 11 and supplies high frequency components from the Push-pull amplifier 12, if it is assumed that frequency components below 3MHz are supplied from the DC / DC converter 11, while letting the Push-pull amplifier 12 provide components of 3 MHz or higher, it can be seen from figure 15 that 90% of the power is supplied by the Power supply circuit 4 is supplied from the DC / DC converter and 10% of the energy is supplied from the Push-pull amplifier 12.
[0062] Energy Conversion Efficiency of the Power Supply Circuit for the OFDM Signal: Figure 14
[0063] An explanation will be given of the energy conversion efficiency of the power supply circuit 4 in the case of an OFDM signal.
[0064] The energy conversion efficiency of the DC / DC converter 11 that supplies DC and low frequency components is determined by several factors including the resistance to switching element switching 13, switching loss, direct diode voltage and loss of inductance 14. Let it be na.
[0065] However, the PAPR of the OFDM signal is 8 dB; thus, as can be seen from figure 10, the energy conversion efficiency of the Push-pull amplifier 12 becomes the energy conversion efficiency at the time of the power reduction being -8 dB. Here, the energy conversion efficiency at this point is given as nb.
[0066] Specifically, 10% of the energy to be supplied by the power supply circuit 4 to the main amplifier 6 is supplied from the Push-pull amplifier 12 with the energy conversion efficiency nb, and 90% is supplied from of DC / DC converter 11 with energy conversion efficiency na. Consequently, the energy conversion efficiency ns of the power supply circuit 4 can be calculated by Equation 2. ns = 1 / (10% / nb + 90% / nd). (Eq. 2)
[0067] Assuming nb = 30% and nd = 90%, ns is 75%.
[0068] To improve the energy conversion efficiency of the entire power supply circuit 4, it is necessary to increase the efficiency of the Push-pull amplifier 12 which is low in energy conversion efficiency.
[0069] In the traditional Push-pull amplifier 12, the voltages of the DC voltage source 23 and DC voltage source 24 that are connected to the collector terminals of transistor NPN 17 and transistor PNP 18 are, respectively, constant, regardless an output level; consequently, when the output level decreases, the energy conversion efficiency also decreases. CITATION LIST Non-Patent Literature
[0070] Non-Patent Literature 1: "An Improved Power-Added Efficiency 19-dBm Hybrid Envelope Elimination and Restoration Power Amplifier for 802.11g WLAN Applications”, Feipeng Wang et al., IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 12, December 2006, pages 4086-4099.
[0071] Non-Patent Literature 2: "A Class B Switch-Mode Assisted Linear Amplifier", Geoffrey R. Walker, IEEE Transactions on Power Electronics, Vol. 18, No. 6, November 2003, pages 1278-1285. SUMMARY OF THE INVENTION Technical problem
[0072] However, the traditional Push-pull amplifier is faced with a problem that follows: the energy conversion efficiency decreases with a reduction in the output level, because the voltages of the DC voltage sources connected to the collector terminals of the transistors NPN and PNP are located at a constant level regardless of the output level.
[0073] Note here that Non-Patent Literature 1 and 2 are silent about any techniques for adjusting the voltages of the DC voltage sources connected to the collector terminals of the NPN and PNP transistors in accordance with the output level.
[0074] The present invention was conceived in view of the current situation, and its objective is to provide a power supply circuit, which adjusts the voltages of the DC voltage sources connected to the collector terminals of the NPN and PNP transistors of a Push-pull amplifier in accordance with an output level to ensure that energy conversion efficiency does not decrease even when the output level goes down. Solution to the Problem
[0075] To solve the problem of the prior art mentioned above, the present invention provides a power supply circuit used for power amplification, which includes a Push-pull amplifier unit to amplify an input signal by Push-amplification schemes pull, a variable power supply unit, responsive to a control signal, to vary the voltage level of a power supply voltage to be provided for the Push-pull amplifier unit, a time delay adjustment unit the input signal fed to the Push-pull amplifier unit, and a control unit that emits a control signal to control the voltage level of the current supply voltage based on the input signal, characterized by the fact that the unit control unit operates, in the case of potential increase of the control signal, to raise the control signal in an anticipated delay, adapted for a transition time of switching the voltage level with respect to a delay time in the timing adjustment unit and, in the event of a drop in the control signal, causes the control signal to drop by a delay time delay.
[0076] Another feature of the present invention is that in the aforementioned power supply circuit, the control unit stores, as a delay delay time, a length of time obtained by subtracting the transition time from the switching time. delay of the timing adjustment unit in a manner corresponding to the switching of the rise and fall voltage level of the control signal and, in the case of rise of the control signal, raise the control signal by a delay that is delayed from the input signal timing by said timing delay time.
[0077] Another feature of the present invention is that in the current supply circuit, the control unit stores a transition gradient of the voltage level corresponding to the switching of the elevation of the control signal and calculates, in the case of elevation of the control, a delay to raise the control signal based on a detected input signal and the gradient, thus causing the control signal to potentially rise in this calculated delay.
[0078] Another feature of the present invention is that, in the current supply circuit, the control unit stores a voltage level transition gradient corresponding to the drop switching of the control signal and the switching of elevation, in the case of control signal drop, a control signal drop delay based on a detected input signal and the gradient, replacing processing to cause the control signal to fall on the delay time delay, thus forcing the control signal falls within the calculated timing.
[0079] The present invention also provides a power amplifier of the type employing the ET scheme, which includes an envelope wave detector to perform wave detection of an input signal, the power supply circuit, mentioned above, with a class D circuit, being provided in an output stage of the Push-pull amplifier unit, and a main amplifier to amplify a signal fed to it, characterized by the fact that the current supply circuit provides for said main amplifier with a power supply voltage adapted to an envelope curve detected by the envelope wave detector.
[0080] The present invention also provides a power amplifier of the type that uses the EER scheme, which includes an envelope wave detector to perform wave detection of an input signal, the power supply circuit, mentioned above, with a class D circuit provided in the output stage of the Push-pull amplifier unit, a main amplifier to amplify a fed signal, and a limiting amplifier that limits the voltage of an input signal and outputs it to the main amplifier, characterized due to the fact that the current supply circuit supplies the main amplifier with a power supply voltage adapted to an envelope curve detected by the envelope wave detector. Advantageous Effects of the Invention
[0081] According to the present invention, the current supply circuit used for power amplification is arranged to include a Push-pull amplifier unit, which amplifies an input signal by Push-pull amplification schemes, a variable power supply, responsive to a control signal to vary the voltage level of a power supply voltage that is provided for the push-pull amplifier unit, a timing adjustment unit that slows the input signal fed to the Push-pull amplifier unit, and a control unit that emits a control signal to control the voltage level of the current supply voltage based on the input signal, at which the control unit operates, in the event of potential of the control signal, to raise the control signal at an early delay, adapted for a voltage level switching transition time with respect to a delay time at the unit timing adjustment and, in the event of a drop in the control signal, causes the control signal to drop in a delay time delay; therefore, there are effects of reducing the influence of the transition time required to raise the voltage level, without having to lower the energy conversion efficiency even when the output level decreases, making it possible to provide a current supply voltage while maintaining the rhythm with, or "tracking", the elevation waveform of an output signal, improving efficiency while simultaneously preventing saturation in the amplifier unit, and allowing for the improvement of distortion characteristics of the output signal.
[0082] In addition, according to the present invention, the current supply circuit is arranged so that the control unit stores, as the delay delay time, a length of time obtained by subtracting the transition time from of the delay time of the timing adjustment unit in a manner corresponding to the switching of the rise and fall voltage level of the control signal and, in the case of rise of the control signal, raise the control signal in a delay that is delayed from the input signal timing by said timing delay time; thus, there is an effect of making it possible to easily perform the processing to raise the control signal at a time earlier than the output signal for a length of time equivalent to the transition time.
[0083] Additionally, according to the present invention, the current supply circuit is arranged so that the control unit stores the gradient of a voltage level transition corresponding to the switching of the control signal elevation and calculates, in the in case of elevation of the control signal, a delay to raise the control signal based on a detected input signal and the gradient, thus causing the control signal to potentially rise in this calculated delay; thus, there are effects of elevating the control signal at an appropriate timing based on the current signal waveform, allowing a supply voltage to also track a broadband signal containing steep elevation, and making it possible to improve the distortion characteristics of the output signal.
[0084] In addition, according to the present invention, the current supply circuit is arranged so that the control unit stores the gradient of a voltage level transition corresponding to the switching of the control signal drop and calculates, in the in the event of a control signal drop, a control signal drop delay based on a detected input signal and the gradient replacing the processing, to cause the control signal to drop in the delay time delay, thus forcing the control signal to drop at the calculated timing; thus, there are effects of dropping the control signal at an appropriate timing based on the actual signal waveform, allowing a supply voltage to also track a broadband signal that contains a steep drop, and making it possible to improve the characteristics of distortion of the output signal.
[0085] Additionally, according to the present invention, the ET power amplifier is arranged to include an envelope wave detector to perform wave detection of an input signal, the above mentioned power supply circuit, with a class D circuit being provided in an output stage of the push-pull amplifier unit, and a main amplifier to amplify a signal fed to it, in which the current supply circuit supplies said main amplifier with a voltage of power supply adapted to an envelope curve detected by the envelope wave detector; thus, there are effects of making it possible to supply a supply voltage that successfully tracks the rising / falling waveforms of the output signal, improving the efficiency of a whole power amplifier, while simultaneously allowing for the improvement of the distortion characteristics of the power amplifier. exit sign.
[0086] Additionally, according to the present invention, the power amplifier of the EER scheme is arranged to include an envelope wave detector to perform wave detection of an input signal, the above mentioned power supply circuit, with a class D circuit provided in the output stage of the push-pull amplifier unit, a main amplifier to amplify a fed signal, and a limiting amplifier that limits the voltage of an input signal and outputs it to the main amplifier, wherein the current supply circuit supplies the main amplifier with a power supply voltage adapted to an envelope curve detected by the envelope wave detector; thus, there are effects of making it possible to supply a supply voltage that successfully tracks or follows the rising / falling waveforms of the output signal, improving the efficiency of an entire power amplifier, while simultaneously allowing for the improvement of the characteristics of distortion of the output signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0087] Figure 1 is a configuration diagram of a Push-pull amplifier for use in a power supply circuit according to the first embodiment of the present invention.
[0088] Figure 2 is an explanatory diagram showing an example of switching control signals in the first Push-pull amplifier and a transistor collector voltage associated with them together with an output waveform.
[0089] Figure 3 is an explanatory diagram showing the power conversion efficiency characteristics of the first Push-pull amplifier.
[0090] Figure 4 is a block diagram showing an example of a DC voltage source circuit configuration, which supplies DC voltage to the collector terminal of an NPN 17 transistor.
[0091] Figure 5 is an explanatory diagram showing a relationship of an output signal waveform and collector terminal voltage in the absence of a transition time.
[0092] Figure 6 is an explanatory diagram showing a transition time of the collector voltage of the transistor NPN 17.
[0093] Figure 7 is a configuration diagram of a Push-pull amplifier for use in a power supply circuit according to the second embodiment of the present invention.
[0094] Figure 8 is an explanatory diagram showing control timings of switching control signals on the second push-pull amplifier.
[0095] Figure 9 is an explanatory diagram showing the input / output signal ratio of the second push-pull amplifier and a collector voltage.
[0096] Figure 10 is an explanatory diagram in case of linear approximation of a gradient in the collector voltage saturation state.
[0097] Figure 11 is an explanatory diagram showing a configuration of another Push-pull amplifier used in the second power supply circuit.
[0098] Figure 12 (a) is a schematic configuration diagram showing an ET power amplifier, and (b) is a schematic configuration diagram showing an EER power amplifier.
[0099] Figure 13 is a configuration diagram showing an example of a power supply circuit that operates at high speeds.
[00100] Figure 14 is an explanatory diagram showing the power conversion efficiency characteristics of a Class B amplifier.
[00101] Figure 15 is an explanatory diagram showing an example of cumulative probability density distribution of an envelope signal in the OFDM signal.
[00102] Figure 16 is an explanatory diagram showing a method for calculating the elevation timing of a switching control signal C1.
[00103] Figure 17 is an explanatory diagram showing a method for calculating the fall delay of the switching control signal C1. DESCRIPTION OF THE MODALITIES
[00104] Modalities of the present invention will be described with reference to the attached drawings below. Summary of Modalities
[00105] A power supply circuit according to one embodiment of the present invention is configured so that a push-pull amplifier includes first and second power supply voltage generation circuits, each having a series connection of one plurality of circuit blocks, each of which has a switch series connection and a DC supply voltage source and also has a diode being connected in parallel with this series connection, in which the first and second generation circuits power supply voltage connectors are connected to collector terminals of the NPN and PNP transistors, respectively, and where a switching control unit is operatively responsive to an input signal level to provide a control signal that controls the connection / switching off switches used to connect DC voltage sources of the plurality of blocks to the collector terminal of the NPN transistor or to the PNP transistor and to control r the collector voltages of the NPN and PNP transistors in accordance with the input signal level, in order to make it possible to allow the collector voltage to track an output level and also to obtain an operation close to saturation even in the cases in which at which the output level is low, so it is possible to improve the energy conversion efficiency of an entire current supply circuit.
[00106] In addition, a power supply circuit according to an embodiment of the present invention is such that a timing adjustment unit is further provided in the power supply circuit, mentioned above, in which the power adjustment unit timing delays the input signal for a predetermined length of time and in which the switching control unit increases the potential of the control signal at a time earlier than the delay time for a time equivalent to the switching transition time level adapted to the voltage level of the collector voltage, in the case of switching of the control signal that controls the on / off of each switch; thus, it is possible to reduce the influence of the transition time, required to change the collector voltage level, thus allowing the improvement of the distortion of the output waveform of the current supply circuit.
[00107] In addition, a power supply circuit according to an embodiment of the present invention is such that the switching control unit in the power supply circuit, mentioned above, is arranged to calculate a rise or fall time delay of the control signal based on both the pre-stored level shift gradient adapted to the collector voltage level and a detected input signal level and then causes the control signal to rise or fall at such a delay; thus, it is possible to determine the output timing of the control signal based on the current signal waveform, thus allowing the improvement of the distortion of the output waveform of the current supply circuit. First Mode: figure 1
[00108] A power supply circuit according to the first embodiment of the present invention includes a Push-pull amplifier and a DC / DC converter, as in the additional power supply circuit, shown in figure 13.
[00109] The current supply circuit according to the first mode of this invention will be explained using figure 1. Figure 1 is a configuration diagram of the Push-pull amplifier used in the current supply circuit according to the first mode of this invention.
[00110] As shown in figure 1, the Push-pull amplifier (first Push-pull amplifier) used in the current supply circuit (first power supply circuit) according to the first modality of this invention includes, as components similar to those of the traditional Push-pull amplifier, shown in figure 13, an input terminal 8, an output terminal 10, an operational amplifier 16, a polarization circuit consisting of resistor 19, diodes 20-21 and resistor 22, a Push- pull constituted from transistor NPN 17 and transistor PNP 18, and DC voltage sources 23-24. A component similar to the traditional Push-pull amplifier corresponds to the Push-pull amplifier unit, as claimed.
[00111] And, as a characterizing part of the first Push-pull amplifier, it has a switching control unit 83, a series combination of DC voltage source 81 and plural circuit blocks B1 to B4, which is connected to the collector of transistor NPN 17, and a series connection of DC voltage source 82 and plural circuit blocks B5 to B8, which is coupled to the collector of transistor PNP 18.
[00112] The voltages of the DC voltage sources 81-82 are given by V9 and V10, respectively.
[00113] The DC voltage source 81 and plural circuit blocks B1-B4 together with the DC voltage source 82 and plural circuit blocks B5-B8 correspond to the variable power supply unit, as claimed.
[00114] Circuit Blocks B1-B4
[00115] Configurations of circuit blocks B1-B4 on the NPN17 transistor side will now be explained.
[00116] Circuit blocks B1-B4 have DC voltage sources (51-54), switches (61-64) and diodes (71-74), respectively. In each block, the "-" side (the negative side) of the DC voltage source is connected to the anode of its associated diode, and the "+" side (positive side) of the DC voltage source is coupled to the cathode through associated switch.
[00117] In addition, the anode of diode 71 of circuit block B1 is connected to earth, and its cathode is coupled to the anode of diode 72 of circuit block B2. In a similar manner, the following diodes 73-74 of circuit blocks B3-B4 are connected in series, allowing the cathode of circuit block B4 to be connected to the "-" side (the negative side) of the DC voltage source 81 .
[00118] The circuit configured from the circuit blocks connected in series B1-B4 is called the first power supply voltage generation circuit.
[00119] And switches 61-64 are controlled on / off by switching control signals C1-C4 from a switching control unit 83, to be described later. The voltage of the DC voltage source of a circuit block with its switch on and the voltage of the DC voltage source 81 are added together, so that a voltage that is positive relative to a reference voltage is applied to the terminal. collector of the NPN 17 transistor.
[00120] In short, the DC voltage source, selected by switch, and DC voltage source 81, become connected in series.
[00121] Note here that voltages from DC voltage sources 51, 52, 53 and 54 of circuit blocks B1-B4 are given by V1, V2, V3 and V4.
[00122] Circuit Blocks B5-B8
[00123] Similarly, circuit blocks B5-B8 on the PNP 18 transistor side have DC voltage sources (55-58), switches (65-68) and diodes (75-78), respectively. In each block, the "-" side of the DC voltage source is connected to the diode anode, and the "+" side of the DC voltage source is connected through the switch next to its cathode.
[00124] The cathode of diode 78 of circuit block B8 is coupled to earth; its anode is connected to diode 77 cathode of circuit block B7. In this way, the following diodes 76, 75 of the circuit blocks B6, B5 are connected in series, allowing the anode of the circuit block B5 to be connected to the "+" side of the DC voltage source 82.
[00125] The circuit configured from the circuit blocks connected in series B5-B8 is called the second power supply voltage generation circuit.
[00126] The first power supply voltage generation circuit and the second power supply voltage generation circuit correspond to the variable power supply unit, as claimed.
[00127] And, switches 65-68 are controlled on / off by switch control signals C5-C8 from switch control unit 83 to be described later. The voltage of the DC voltage source of a circuit block with its switch on and the voltage of the DC voltage source 82 are added together, so a negative voltage in relation to the reference voltage is applied to the collector terminal of the transistor PNP 18.
[00128] In short, the DC voltage source, selected by switch, and the DC voltage source 82 are connected in series.
[00129] Note that the voltages of DC voltage sources 55, 56, 57 and 58 of circuit blocks B5-B8 are given as V5, V6, V7 and V8, respectively.
[00130] The switching control signals C1-C4 and C5-C8 correspond to the control signals mentioned in the claims.
[00131] Switching Control Unit 83
[00132] An explanation will be given below of the switching control unit 83 - this is a characterizing part of the first Push-pull amplifier.
[00133] The switching control unit 83 emits, based on a signal (envelope signal) fed from the input terminal 8, switching control signals C1, C2, C3, C4 to respectively control the on / off of switches 61, 62, 63, 64 of circuit blocks B1, ..., B4, in such a way that the voltage applied to the collector terminal of transistor NPN 17 is set to an appropriate value.
[00134] Similarly, switching control unit 83 emits, based on the envelope signal, switching control signals C5, C6, C7, C8 to respectively control the on / off of switches 65, 66, 67, 68 of circuit blocks B5, ..., B8 to ensure that the voltage applied to the collector terminal of the PNP transistor 18 is set to an appropriate value.
[00135] More specifically, the switching control unit 83 has a control signal generation circuit that emits eight types of switching control signals after having adjusted one of them or to a high level (level H, ON ) or low level (level L, OFF), which circuit emits each switching control signal having level H or level L based on the fed envelope signal.
[00136] Each control signal generation circuit of switching control unit 83 is constituted from a comparator circuit, for example.
[00137] With this arrangement, it is possible in the first Push-pull amplifier to apply a collector voltage tracking the output voltage to the transistor NPN 17 and transistor PNP 18 in response to a change in the power level of the input signal, thus improving the energy conversion efficiency of the Push-pull amplifier, thus making it possible to improve the efficiency of an entire current supply circuit. Operation of the First Push-pull Amplifier: figure 1
[00138] First, the operations of circuit blocks B1-B4 and B5-B8 will be explained briefly.
[00139] In each of the circuit blocks B1-B4 and B5-B8, the anode terminal of the diode is connected to the negative side of the DC voltage source, while the cathode node is connected to the positive side of the power source. DC voltage. By serially connecting such circuit blocks B1-B4, B5-B8 and controlling the on / off of each switch, it is possible to apply a voltage added to the collector terminal of transistor NPN 17, the PNP transistor 18.
[00140] In case the switch is turned on, the voltage from the DC voltage source of the circuit block is added, causing a current to flow in the DC voltage source; thus, the circuit operates. At this time, no current flows in the diode, as there is a reverse voltage in the forward direction.
[00141] Alternatively, in case the switch is turned off, the DC voltage source of the circuit block becomes open circuit; thus, adding voltage is not done, but current flows in the diode, resulting in no circuit being made operational.
[00142] And, in the first Push-pull amplifier, the switching control unit 83 emits, in accordance with the envelope signal fed from the input terminal 8, switching control signals C1-C8 after having changed the level of each signal or to level H or level L, thus controlling the switching on / off of the switches of the corresponding circuit blocks.
[00143] With this, a collector voltage that is positive in relation to the reference voltage is applied to the NPN 17 transistor, and a collector voltage that is negative in relation to the reference voltage is applied to the PNP transistor 18 in accordance with input power level. Switching Control Signal and Transistor Collector Voltage: figure 2
[00144] An explanation will be given below, using figure 2, of a switching control signal ratio in the first Push-pull amplifier and transistor collector voltage. Figure 2 is an explanatory diagram showing an example of switching control signals on the first Push-pull amplifier together with the resulting collector voltage and transistor output waveform.
[00145] In (a) of figure 2, an example set of switching control signals C1-C8 is shown, to indicate whether each of the switching control signals C1-C8 is in the state in which it causes its corresponding switch turns on (level H) or in the state that causes the switch to turn off (level L).
[00146] 0066 In the example of figure 2 (a), the switching control signal C1 is at level L within a period of up to a time point T1, is situated at level H in a period of time point T1 to time point T8, and moves to level L again after time point T8.
[00147] As for the switching control signal C8, it is at level L in a period up to time point T12, it is located at level H in a period from time point T12 to time point T13, and becomes level L after time point T13.
[00148] Shown in figure 2 (b) are a collector voltage (node voltage A) for transistor NPN 17, a collector voltage (node voltage B) for transistor PNP 18, and an output voltage waveform in the case of the switching control signals C1-C8 from (a) being provided for the same. The reference voltage is set to zero (0), for example.
[00149] As previously mentioned, in the first Push-pull amplifier, when the switching control signals C1-C8 are at level H, their corresponding switches 61-68 turn on.
[00150] In figure 2, an explanation will be given first while focusing attention on the tension of node A.
[00151] Within a period from time point 0 to time point T1, all of the switching control signals C1-C4 are at level L; thus, switches 61-64 are all turned off.
[00152] Consequently, no current flows in the voltage sources of DC 51- 54; however, current flows at diodes 71-74, resulting in the voltage from the DC voltage source 81 V9 being applied to node A.
[00153] Note that, in this mode, an explanation of it assumes that the direct voltage of diodes 71-78 is zero.
[00154] Subsequently, within a period from time point T1 to time point T2, only switching control signal C1 is at level H, with the other switching control signals C2-C4 being located at level L; thus, only switch 61 is turned on.
[00155] As the DC voltage source 51 corresponding to switch 61 and the DC voltage source 81 are connected in series, the voltage of node A becomes V9 + V1.
[00156] That is, in short, the voltage of the DC voltage source of a circuit block with its switch being turned on is added to the voltage V9 of the DC voltage source 81, resulting in this processed voltage in addition being applied to the node THE.
[00157] From now on, similarly, when switching control signals C2, C3, C4 become level H at time points T2, T3, T4, switches 62, 63, 64 turn on in response to them, respectively. Thus, voltages V2, V3, V4 are additionally added to the voltage of node A.
[00158] In addition, switching control signals C4, C3, C2, C1 go to level L at time points T5, T6, T7, T8, causing switches 64, 63, 62, 61 to turn off , respectively; thus, the voltage of node A is subtracted from the voltages V4, V3, V2, V1, as shown in figure 2.
[00159] With respect also to the voltage of node B, as in the case of node A, switches 65-68 controlled by switching control signals C5-C8 are switched to ON or OFF, thus obtaining a change, as shown in the figure 2. The voltage of node B that varies within the period from time point T9 to time point T16 is opposite in positive / negative polarities to the voltage of node A in time period T1-T8. Operation of the Switch Control Unit 83: figures 1-2
[00160] Next, an operation of the switching control unit 83 will be explained using figures 1 and 2.
[00161] As mentioned above, the switching control unit 83 changes, based on an envelope signal detected from the input signal, the potential level of each of the switching control signals C1-C8 to the level H or L level and then emit the same.
[00162] As a result, switching control signals C1-C4 for controlling switches 61-64 that control node A voltage vary when the output waveform is positive.
[00163] The switching control unit 83 adjusts, based on a fed envelope signal, the switching control signal C1 at level H when the output waveform voltage is greater than V9.
[00164] In addition, switching control unit 83 adjusts switching control signal C2 at level H, when the output waveform voltage is greater than V9 + V1, adjusting switching control signal C3 at level H when the output waveform voltage is greater than V9 + V1 + V2, and sets the switching control signal C4 to level H when the output waveform voltage is greater than V9 + V1 + V2 + V3.
[00165] Under other conditions, switching control unit 83 adjusts switching control signals C1-C4 at level L.
[00166] Similarly, switching control signals C5-C8 to control switches 65-68 that control the voltage of node B vary when the output waveform is negative.
[00167] Switching control unit 83 adjusts, based on a powered envelope signal, switching control signal C5 to level H, when the voltage of an output waveform is less than -V10, sets the switching control signal C6 to level H, when the output waveform voltage is less than -V10-V5, sets the switching control signal C7 to level H when the waveform voltage of output is less than -V10-V5-V6, and sets the switching control signal C8 to level H, when the output waveform voltage is less than -V10-V5-V6-V7.
[00168] Under the other conditions, the switching control unit 83 sets switching control signals C5-C8 to level L.
[00169] The switching control unit 83 is arranged in such a way that the switching control signals C1-C8 operate under these conditions and is easily accomplished using a comparator circuit. This comparator circuit can be designed to have hysteresis characteristics.
[00170] As shown in figure 1, in the first Push-pull amplifier, the switching control unit 83 is designed in view of the gain of an output level in relation to the output level, in order to generate switching control signals C1- C8 from an envelope signal fed from input terminal 8.
[00171] The voltages V1 to V10 of the respective DC voltage sources can be adjusted to the same voltage value or, alternatively, they can be adjusted to different voltage values.
[00172] Also, note that although the voltages of nodes A and B are each arranged here to vary in five stages, it is permissible to modify them to have other numbers of stages.
[00173] Furthermore, although in the first Push-pull amplifier the output waveform is compared with a limit value to which addition or subtraction was applied in combination of V9, V1, V2, V3, V4 or V10, V5, V6 , V7, V8 to determine the level of each switching control signal (H or L), it is not always necessary to do this. Efficiency of the First Push-pull Amplifier: figure 3
[00174] Next, the efficiency of the first push-pull amplifier will be explained using figure 3. Figure 3 is an explanatory diagram showing the power conversion efficiency characteristics of the first push-pull amplifier.
[00175] As previously mentioned, in the first Push-pull amplifier, the voltage of the collector terminal (node A) of the transistor NPN 17 and the voltage of the collector terminal (node B) of the transistor PNP 18 vary according to the form of output wave.
[00176] In other words, the voltages of nodes A and B are controlled to also make the absolute value of the collector terminal voltage smaller when the output waveform is small, so the first Push-pull amplifier always operates in one near the saturation output.
[00177] Consequently, as shown in figure 3, the energy conversion efficiency of the first Push-pull amplifier increases when compared to the previous art proposal, shown in figure 14. Especially, at a lower output than the output of saturation, the efficiency improvement is remarkable.
[00178] For example, the energy conversion efficiency at the time of the power reduction = -8 dB corresponding to the OFDM signal is improved by 55% in the first Push-pull amplifier, although it was 30% in the Push amplifier conventional pull of figure 14. DC voltage source circuit configuration: figure 4
[00179] An explanation will be given below, using figure 4, of a configuration of the DC voltage source circuit, which supplies DC voltage to the collector terminal of transistor NPN 17 or to transistor PNP 18. Figure 4 is a block diagram showing an example of a DC voltage source circuit configuration that supplies DC voltage to the collector terminal of the NPN 17 transistor. Note that the same reference numbers are assigned to portions corresponding to the DC voltage sources 51 -54 shown in figure 1.
[00180] Although only the DC voltage source circuit on the NPN17 transistor side is explained here, the DC voltage source circuit on the PNP 18 transistor side is also similar in configuration.
[00181] As shown in figure 1, the DC voltage sources 51-54 and the DC voltage source 81 are connected in series when switches 61-64 are activated for the connection; DC voltage sources 55-58 and DC voltage source 82 are connected in series when switches 65-68 are turned on. Thus, it is necessary to employ an isolated power supply project.
[00182] As shown in figure 4, the DC voltage source circuit of the first Push-pull amplifier includes an input terminal 201 for power supply, a straightening circuit 202 that performs the smoothing of the current supply voltage powered from input terminal 201, a switching circuit 203, a transformer 204 for electrical isolation between an input and a plurality of outputs, rectification / smoothing circuits 205-208 that perform the rectification and smoothing of the output voltage, an error amplifier 209 that detects an error from a target output voltage, a photocoupler 210 to establish isolation when passing error information to the control circuit, a control circuit 211 that minimizes the error information, to provide control for retention at the target output voltage, and a drive circuit 212 to drive switching circuit 203.
[00183] An operation of the DC voltage source circuit with the above mentioned configuration will be explained.
[00184] When a Vin voltage is fed from the input terminal 201, it is smoothed by the smoothing circuit 202 and fed to the input side of the transformer 204 through the switching circuit 203.
[00185] On the output side of transformer 204, coils are provided, which have numbers of turns corresponding to the voltage values of the respective DC voltage sources 51-54. The voltages converted depending on the number of turns are applied through the 205-208 rectifying / smoothing circuits, thus becoming output voltages from the DC voltage sources 51-54, respectively.
[00186] The voltages of the DC voltage sources 51-54 are V1-V4, in which control is provided so that the DC voltage source 54 reaches its target value V4.
[00187] More specifically, the control for setting the target voltage V4 is obtained by monitoring the DC voltage source 54, by feeding an error signal, which is a difference between the voltage of the DC voltage source 54 that was detected by the error amplifier 209 and the target voltage, for the control circuit 211 through the photocoupler 201, and by causing the control circuits 211 to vary the operating relationship of a signal for switching on / off the circuit switching value 203 in such a way that the error signal becomes smaller.
[00188] Although no monitoring is performed for DC voltage sources 51-53, the number of turns of transformer 204 can be designed to ensure that voltages from DC voltage sources 51, 52, 53, respectively, become if V1, V2, V3, when the voltage of the DC voltage source 54 becomes V4. First Mode Effects
[00189] The current supply circuit according to the first embodiment of the present invention is arranged to include in a Push-pull amplifier a first power supply voltage generation circuit, configured from a series connection of blocks plural circuit B1-B4, each having a switch and DC voltage source, being connected in series, and also having a diode being connected in parallel with them, and a second power supply voltage generating circuit having a series connection of plural circuit blocks B5-B8, in which the first power supply voltage generation circuit is connected to the collector terminal of transistor NPN 17, while the second power supply voltage generation circuit is connected to the collector terminal of the PNP transistor 18, and in which switching control unit 83 emits, in response to the envelope signal of an input signal from the aging wave detector eg 3, switching control signals C1-C8 for controlling the on / off of switches 61-68 of circuit blocks B1-B8. Consequently, there are control effects of the collector voltages of the transistor NPN 17 and the transistor PNP 18, depending on the level of the input signal, in such a way as to follow the level of an output signal, making it possible to always achieve near operability to saturation, improving the energy conversion efficiency in the case of low output level of the Push-pull amplifier, and allowing the improvement of the energy conversion efficiency of an entire current supply circuit.
[00190] Another effect is that the use of the first power supply circuit for EER amplifiers, for example, makes it possible to improve the efficiency of the entire amplifier, reduce energy consumption, decrease the radiation fin module, and thus obtain the desired reduction in size and weight.
[00191] It is noted that, although in the above example the DC voltage sources 81, 82 are respectively arranged to always apply their voltages to nodes A, B, this can be modified so that a switch and diode are added to it to allow a circuit block to perform on / off operations in a manner similar to other DC voltage sources.
[00192] Also note that the configurations of the power supply voltage generation circuits, which respectively generate the collector voltages of the transistor NPN 17 and transistor PNP 18 are not limited to those shown in figure 1 and can be modified to employ any other circuit configurations, as long as each provides different voltages depending on the control signals from the switching control unit. Second Mode
[00193] Next, a power supply circuit according to the second embodiment of the present invention will be explained. Example of Collector Voltage with Ignored Transition Time: Figures 1 and 5
[00194] Before explaining the second modality in detail, an explanation will be given, using figures 1 and 5, of the relation of an output signal waveform and collector voltage, in a case in which the transition time does not exists when the potential of the collector voltage transitions from a given level to its next level in the first Push-pull amplifier shown in figure 1. Figure 5 is an explanatory diagram showing the relationship of the output signal waveform and potential collector terminal in the absence of such a transition time.
[00195] Note that in figure 5, a collector voltage is shown, which considers the diode direct voltage of each block.
[00196] As shown in figure 5, a switching control unit 83 emits switching control signals for switching on / off of respective switches 61-68 of the power supply voltage generation circuits, mentioned above, based on a magnitude correlation of limits Vth1- Vth8 and an output voltage waveform 103 of the push-pull amplifier, which is provided for the emitter terminals of transistor NPN 17 and transistor PNP 18.
[00197] Note that in the circuit configuration of figure 1, the switching control unit 83 generates, based on the envelope signal of an input signal, each switching control signal adapted to the relationship between output voltage / limit .
[00198] As a result, assuming that there is no transition time in the case of switching the collector voltage, the collector voltage of the NPN 17 transistor has a waveform indicated by 101, while the collector voltage of the PNP transistor 18 has a waveform shown by 102.
[00199] Here, letting the direct voltages of diodes 71-78 be VF1, VF2, VF3, VF4, VF5, VF6, VF7, VF8, respectively, in an example case where only switches 61 and 62 shown in figure 1 are in the ON state and the other switches are in the OFF state, current flows into the NPN 17 transistor through DC voltage sources 51, 52, diodes 73, 74 and DC voltage source 81.
[00200] The voltage Vc At the collector terminal of transistor NPN 17 in this case is given by: Vc = V1 + V2 + V9-VF3-VF4.
[00201] Additionally, since the transistor NPN 17 and transistor PNP 18 are operating as push-pull circuit, a potential difference between the collector and emitter terminals of transistor NPN 17 is required to be significant to an extent where the transistor NPN 17 is not saturated within a period of time in which transistor NPN 17 is operating. Similarly, within a PNP 18 transistor operating period, a potential difference between the collector and emitter terminals of the PNP 18 transistor is required to be sufficiently large.
[00202] When the potential difference between the collector and emitter terminals becomes less than the saturation voltage of the transistor, the transistor is saturated, resulting in a distortion that appears in a signal provided from the push-pull amplifier .
[00203] Consequently, as shown in figure 5, the limits (Vth1 to Vth8) for judging the level of a push-pull amplifier output waveform are adjusted as follows: Vth1 <V9-VF1-VF2-VF3- VF4-Vce (npn: sat), Vth2 <V9 + V1-VF2-VF3-VF4-Vce (npn: sat), Vth3 <V9 + V1 + V2-VF3-VF4-Vce (npn: sat), Vth4 <V9 + V1 + V2 + V3-VF4-Vce (npn: sat), Vth5> -V10 + VF5 + VF6 + VF7 + VF8 + Vce (pnp: sat), Vth6> -V10-V5 + VF6 + VF7 + VF8 + Vce (pnp: sat), Vth7> -V10-V5-V6 + VF7 + VF8 + Vce (pnp: sat), Vth8> -V10-V5-V6-V7 + VF8 + Vce (pnp: sat).
[00204] Here, Vce (npn: sat) is the collector-emitter voltage for saturation of transistor NPN 17, and Vce (pnp: sat) is the collector-emitter voltage for saturation of transistor PNP 18.
[00205] With this proposal, even when any collector voltage value is selected by the control signal from switching control unit 83, it is possible to guarantee the differences in collector-emitter potential of the transistor NPN 17 and transistor PNP 18 to the extent that no transistor saturation occurs. Collector Voltage transition time: figure 6
[00206] An explanation will be given below, using figure 6, of the transition time of the collector voltages applied to the collectors of transistor NPN 17 and transistor PNP 18. Figure 6 is an explanatory diagram showing the transition time of the voltage of collector of the NPN 17 transistor.
[00207] Shown in figure 6 are an ideal waveform 111 of the collector voltage of transistor NPN 17 with respect to an example of the output waveform 113 of the Push-pull amplifier 12 and an example of current waveform 112.
[00208] In the EER power supply circuit, the collector voltage is forced to change, while keeping pace with, or "tracks", a change in output waveform 113 of the Push-pull amplifier 12.
[00209] In the example of figure 6, control is provided to change, at a time point t, the collector voltage potential level from Vc (i) to the next voltage level Vc (i + 1) with an increase in the level of the output waveform 113 of the push-pull amplifier and then changes it to the voltage level Vc (i) again in response to a decrease in level of the output waveform 113.
[00210] At time point t, in response to receiving an instruction from switch control unit 83, one of switches 61-65 changes to its ON state from the OFF state, causing the voltage applied to the collector node of transistor NPN 17 changes from Vc (i) to Vc (i + 1); in this case, if the transition time for the voltage level transition is unnecessary, it becomes a waveform similar to stairs steps, which resembles the ideal signal waveform 111.
[00211] However, the current signal waveform 112 is a response that accompanies a finite switching time (transition time) Δt, as shown in figure 6. A collector voltage switching waveform on the PNP transistor 18 it is a top-down inverted version of the 112 waveform.
[00212] Broadband Signal Case
[00213] Note here that, in cases where the signal fed to the Push-pull amplifier 12 is a W-CDMA signal or a broadband OFDM signal, it sometimes happens that such signal has steep rise and fall edges, as shown by the output waveform 113.
[00214] In this case, if the switching of the collector voltage is delayed, a difference between the collector node and emitter potentials of the push-pull amplifier goes below the saturation voltage, and then the transistor saturation takes place, resulting in unwanted generation of a distortion in the output signal waveform of the Push-pull amplifier 12.
[00215] Transition Time Reduction
[00216] To avoid this, it is necessary to reduce the transition time of the potential level of the collector voltage.
[00217] The transition time is determined by response speeds of switches 61-68 and switching control unit 83 and by parasitic capacitance / inductance components, inherent to the respective parts of the circuit. in view of this, a certain degree of improvement can be obtained by optimizing the circuit design with the use of response speed improving elements and / or elements that worsen the parasitic inductance / capacitance.
[00218] However, it was still difficult to shorten the transition time sufficiently to allow a response to the steep rise and fall of the broadband signal envelope signal.
[00219] In addition, when an attempt is made to steeply change the voltage level in order to reduce the transition time, the collector voltage can sometimes suffer the occurrence of the so-called transient oscillation, such as rupture or variations amplitude ripples: if such a transient oscillation is large, the emitter-collector potential difference becomes smaller, resulting in a distortion that tends to appear in the output signal.
[00220] In short, it was difficult to sufficiently reduce the collector voltage transition time, while simultaneously allowing the transient oscillation to lie within an allowable range.
[00221] Consequently, in the second embodiment of this invention, a power supply circuit is provided, capable of successfully tracking a change in level of the broadband signal even when the transition time in switching events of collector voltage is a length of time that causes the transient oscillation to fall within the allowable range, thus preventing the degradation of the distortion characteristics of the output signal. Second Mode Configuration: figure 7
[00222] The current supply circuit according to the second embodiment of the present invention includes a Push-pull amplifier and the DC / DC converter in a similar manner to the first power supply circuit.
[00223] A configuration of the Push-pull amplifier used in the current supply circuit according to the second modality of this invention will be explained using figure 7. Figure 7 is a configuration diagram of the Push-pull amplifier used in the supply circuit current according to the second embodiment of this invention.
[00224] As shown in figure 7, the Push-pull amplifier (second Push-pull amplifier) used in the current supply circuit (second power supply circuit) according to the second modality of this invention is similar, in the basic configuration , to the first power supply circuit shown in figure 1; thus, an explanation will be given by adding the same numerals to the same parts of figure 1.
[00225] The second Push-pull amplifier is characterized by, in a new way, having a timing control unit 121; in addition, the configuration and operation of the switching control unit 83 'are partially different from those of the switching control unit 83 of the first push-pull amplifier. Operation Summary of the Second Push-Pull Amplifier
[00226] Here, an operation of the second Push-pull amplifier will be explained shortly.
[00227] The second Push-pull amplifier is one that sufficiently delays an input signal by taking into account the collector voltage transition time to allow the collector voltage to successfully track even when a broadband signal is fed.
[00228] More precisely, the second Push-pull amplifier feeds the signal fed to the operational amplifier 16 after having slowed it down by a constant delay time (td) that is greater than the transition time of the collector voltage, and causes with that the control signals C1-C8 generated based on a non-delayed input signal potentially rise with a delay corresponding to a length of time (td-Δt) obtained by subtracting the collector voltage transition time (Δt) to from the delay time (td).
[00229] By this means, switching control signals C1-C8 are provided in a more preceding delay than an output signal at the emitter terminal of the transistor for the transition time (Δt), thus allowing the collector voltage to vary , while tracking the same when a steep change occurs in the input signal, thus making it possible to prevent degradation of the distortion characteristics of the output signal.
[00230] Note that, in reality, the collector voltage transition time is a time that differs by voltage level.
[00231] Each Part of the Second Push-pull Amplifier
[00232] The characteristic part of the second Push-pull amplifier will be explained concretely.
[00233] Timing control unit 121
[00234] Timing control unit 121 delays a fed signal from input terminal 8 for a specific pre-set delay time td and then outputs it to operational amplifier 16.
[00235] The delay time td is determined to be a length of time that is longer than the transition time at any voltage level of the collector voltage.
[00236] Timing control unit 121 corresponds to the timing adjustment unit, as claimed.
[00237] 83 'Switching Control Unit
[00238] Although switching control unit 83 'is one that generates switching control signals C1-C8 based on an envelope signal fed from input terminal 8 in a similar manner to switching control unit 83 in the first Push-pull amplifier, it delays the switching control signal output timing (level change) when compared to the first Push-pull amplifier.
[00239] The switching control unit 83 'has a comparator circuit that generates switching control signals C1-C8 and, in addition, a control circuit that controls the timing of the emission of switching control signals C1-C8 generated. This control circuit is configured from a microcomputer or similar, which has a processing unit and a storage unit.
[00240] Note that the switching control unit 83 'corresponds to the control unit, as claimed.
[00241] An explanation will be given of the collector voltages of transistor NPN 17 and transistor PNP 18 which are determined by combinations of levels (high and low level) of the switching control signals C1-C8 from the switching control unit 83 '.
[00242] Considered here are the direct voltages (VF1-VF8) of diodes 71-78 of the respective circuit blocks B1-B8.
[00243] Letting the voltages applied to the collector terminal of transistor NPN 17 in the second Push-pull amplifier be given by Vc1-Vc5 and letting the voltages applied to the collector terminal of transistor PNP 18 be Vc6-Vc10, the voltage levels of collector in the circuit configuration of figure 7 have ten stages, which follow: Vc1 = V9-VF1-VF2-VF3-VF4, Vc2 = V9 + V1-VF2-VF3-VF4, Vc3 = V9 + V1 + V2-VF3-VF4 , Vc4 = V9 + V1 + V2 + V3-VF4, Vc5 = V9 + V1 + V2 + V3 + V5, Vc6 = -V10 + VF5 + VF6 + VF7 + VF8, Vc7 = -V10-V5 + VF6 + VF7 + VF8 , Vc8 = -V10-V5-V6 + VF7 + VF8, Vc9 = -V10-V5-V6-V7 + VF8, Vc10 = -V10-V5-V6-V7-V8.
[00244] As previously mentioned, the transition time in collector voltage switching events is different by voltage level. The transition time required for switching from voltage level Vc1 to Vc2 is given as Δt1.
[00245] Similarly, the transition time from voltage level Vc2 to Vc3 is given by Δt2; the transition time from voltage level Vc3 to Vc4 is given as Δt3; the transition time from the voltage level Vc4 to Vc5 is given as Δt4; the transition time from voltage level Vc6 to Vc7 is given as Δt5; the transition time from voltage level Vc7 to Vc8 is given as Δt6; the transition time from voltage level Vc8 to Vc9 is like Δt7; and, the transition time from voltage level Vc9 to Vc10 is like Δt8.
[00246] The values of transition times Δt1, ..., Δt8 are values determined by the characteristics of the push-pull amplifier, characteristics / circuit constants of the respective elements that make up the circuit and also the characteristics of the main amplifier 6 of the amplifier. power, and is a prehensible value at the design stage.
[00247] The switching control unit 83 'of the second Push-pull amplifier pre-stores respective switching levels of the collector voltage (Vc1 ^ Vc2, Vc2 ^ Vc3, ..., Vc9 ^ Vc10) and lengths of time transition (Δt1 to Δt8) necessary for such potential changes in a one-to-one correspondence manner.
[00248] Note here that, the transition time is considered only for potential increase (switching on) of control signals; any transition time in fall events is not considered.
[00249] In other words, the switching control unit 83 'stores, as Δt1-Δt8, the elevation transition time values of the respective switching control signals C1-C8.
[00250] A feature of the second push-pull amplifier is that the switching control unit 83 'has a table that stores length of time (ie delay time delay) to delay the timing for changing the level of signal signals. switching control C1, ..., C8 with respect to each of the collector voltage switching levels.
[00251] In a practical way, the switching control unit 83 'performs the control based on an input signal to the Push-pull amplifier 12, it stores time delay time data in a way corresponding to the magnitude ratio of the input signal and a plurality of preset limits and the direction of a change in the input signal - that is, the rise or fall of each of the switching control signals C1, ..., C8.
[00252] After all, the switching control unit 83 'stores the delay delay time in its memory to delay the timing in rise and fall events with respect to each of the switching control signals C1 ,. .., C8.
[00253] The second push-pull amplifier is such that, in the case of raising the switching control signal (switching switch case), it stores, as the delay delay time, a length of time (td -Δt) obtained by subtracting a transition time corresponding to each switching level from the delay time td in time control unit 121.
[00254] Alternatively, in the event of a drop in the switching control signal, it stores as the delay delay time the delay time td in timer control unit 121.
[00255] As for the timing, the delay time of each switching control signal will be described later. Switching Control Signal Timing on the Second Push-Pull Amplifier: Figure 8
[00256] Next, the timing of the switching control signal on the second Push-pull amplifier will be explained using figure 8. Figure 8 is an explanatory diagram showing switching control signal timing on the second Push-pull amplifier. of figure 2.
[00257] Shown in figure 8 are switching control signals C1-C8, in the case of an input signal 131 being fed from the input terminal 8 of the Push-pull amplifier. When switching control signals C1-C8 are at level L, their corresponding switches 61-68 are in the OFF state; when switching control signals C1-C8 are at level H, the corresponding switches 61-68 are in the ON state.
[00258] The switching control unit 83 'compares the input signal 131 with pre-stored limits Vth1-Vth8 to determine each level (level H or L) of the switching control signals C1-C8 and emits in a time delay delayed by the delay delay time that is pre-stored in a manner corresponding to the magnitude ratio of the input signal 131 and the limit and direction of a change.
[00259] As shown in figure 8, leave a time point, at which the signal waveform 131 becomes greater than the limit Vth1, be t1, and leave a time point at which it becomes greater than Vth2, Vth3, Vth4 are t2, t3, t4, respectively.
[00260] In addition, leave a time point, at which the signal waveform 131 becomes smaller than the limit Vth5, be t9, and leave a time point at which it becomes smaller than Vth6, Vth7, Vth8 be t10, t11, t12, respectively.
[00261] On detection that the signal waveform 131 has become larger than the limit Vth1 at time point t1, the switching control unit 83 'adjusts the switching control signal C1 at level H; on this occasion, the switching control unit 83 'reads from the table a delay delay time that corresponds to the elevation event of the switching control signal C1 and emits a signal with its level changed to level H, in a delay delayed by this delay delay time from time point t1.
[00262] As mentioned above, when td1 is allowed to be the delay time delay in the elevation of the switching control signal C1, td1 is a length of time defined by subtracting the transition time Δt1 in the elevation time of the control signal switching time C1 from the delay time td in the timing control unit 121 (ie ((td1 = td-Δt1)).
[00263] Similarly, switching control unit 83 'delays switching control signals C2-C4 by switching the collector voltage of transistor NPN 17 by delay times td2-td4 from time points t2-t4, respectively, and issues them after changing the level of each signal from level L to level H.
[00264] The switching control unit 83 'also delays the switching control signals C5-C6 for switching the collector voltage of the PNP transistor 18 by the delay times td9-td12 from time points t9-t12 and then changes level from level L to level H.
[00265] The elevation delay time (level L ^ level H) and fall time (H ^ level L) of the respective switching control signals are as follows: C1 Rising: td1 = td-Δt1, C2 Rising -se: td2 = td-Δt2, C3 Rising: td3 = td-Δt3, C4 Rising: td4 = td-Δt4, C4 Lowering: td5 = td, C3 Lowering: td6 = td, C2 Lowering: td7 = td, C1 Lowering: td8 = td, C5 Rising: td9 = td-Δt5, C6 Rising: td10 = td-Δt6, C7 Rising: td11 = td-Δt7, C8 Rising: td12 = td -Δt8, C8 Lowering: td13 = td, C7 Lowering: td14 = td, C6 Lowering: td15 = td, C5 Lowering: td16 = td.
[00266] The switching control unit 83 'has its memory, in which the above mentioned delay delay times are stored and, in a switching control signal switching event, emits an altered signal at level H or L , while slowing it down for a corresponding time delay time.
[00267] When the input signal 131 given to the Push-pull amplifier 12 is caused, by the timing control unit 121, to be delayed by the delay time td and then supplied, the switching control signals are provided, while the delay delay times (td1-td16) are being delayed by the aforementioned; thus, in switching control signal elevation events, it becomes possible to accelerate the switching timing of a voltage applied to the collector terminal for each transition time in relation to the signal waveform at the output terminal of the Push amplifier -pull.
[00268] This makes it possible to reduce the influence of the collector voltage switching transition time when the switching control signal is elevated, responsive to the increase of the input signal potential, thus allowing the suppression of degradation of the distortion characteristics of the output signal. Examples of 2nd Push-pull Amplifier Input and Output Signal and Collector Voltage: figure 9
[00269] Next, a relation of the input / output signal of the second push-pull amplifier and collector voltage will be explained using figure 9. Figure 9 is an explanatory diagram showing the input / output signal ratio of the second Push-pull amplifier and collector voltage.
[00270] For an input signal 131 of the Push-pull amplifier shown in figure 9 (a), an output signal 141 is provided after being delayed by the timing control unit 121 for a predetermined delay time td, as shown in (b).
[00271] Also note that a collector voltage 142 that is applied to the collector terminal of transistor NPN 17, in case the output signal 141 is greater than a reference voltage, is caused by a switching control signal, which potentially it changes with the delay delay time, mentioned above, to carry out the level change in a delay earlier than the arrival of the output signal 141 at its limit; therefore, it varies in steps while following a change in output signal 141.
[00272] Similarly, a collector voltage 143 that is applied to the PNP transistor 18, in the case of output signal 141 being less than the reference voltage, is also caused to vary in steps, while keeping track of a change output signal 141. Effects of the Second Mode
[00273] The current supply circuit according to the second embodiment of this invention is arranged so that the switching control unit 83 'is provided, in place of the switching control unit 83 of the first power supply circuit, the timing control unit 121 is provided to delay an input signal by the specific delay time td, the switching control unit 83 'stores, in a manner corresponding to the respective switching control signals C1-C8, the switching time Δt transition taken for the collector voltage level transition of the transistor NPN 17 or transistor PNP 18 due to the rise / fall of potential of the switching control signals and also stores lengths of delay time of rise / fall delay in a way corresponding to the respective switching control signals C1-C8. Then, the switching control unit operates in the event of elevation of each of the switching control signals C1-C8 to perform H-level change with a delay by a degree of the delay delay time (td-Δt) stored in a manner corresponding to the switching control signal of interest and operates in the event of a drop in the switching control signal to carry out the change of level L with a delay by the delay delay time td from the input signal delay. Thus, there are advantageous effects, that is, it is possible to raise the switching control signal at a time point earlier than the signal that was delayed at the timing control unit 121 by a length of time equivalent to the transition time of the collector voltage in the switching control signal rise time, thus eliminating the influence of the collector voltage transition time and allowing it to track or "follow" any steep elevation of broadband signals, thus making it possible to improve the characteristics distortion of the output signal.
[00274] Additionally, by using the second power supply circuit as a power supply circuit displacement of ET and EER power amplifiers, shown in figure 12, it is possible to supply the main amplifier 6 with a supply voltage of current that successfully tracks the output signal level of the main amplifier 6 and further improve the efficiency of a total of such ET and EER power amplifiers. Third Mode
[00275] A power supply circuit (third power supply circuit) according to a third embodiment of this invention will now be described.
[00276] Although the third power supply circuit is similar in configuration to the second power supply circuit, in that it has a push-pull amplifier and DC / DC converter, the circuit is specifically arranged to determine arithmetically the switching timing of the elevation of the switching control signal in the switching control unit 83 'of the Push-pull amplifier (third push-pull amplifier) 12. Gradient in the Transition State of the Collector Voltage: figure 10
[00277] First, the gradient in the collector voltage transition state will be explained using figure 10. Figure 10 is an explanatory diagram for the linear approximation of the gradient in the collector voltage transition state.
[00278] As shown in figure 10, in a case where the collector voltage potentially changes from a given voltage level Vci to the next voltage level Vc (i + 1), the resulting waveform does not it becomes a rectangular waveform, but it becomes moderate elevation with a transition time Δtj.
[00279] In the example of figure 10, when the gradient in the transition state of the collector voltage is applied linearly, the gradient s is represented by: s = (Vc (i + 1) -Vci) / Δtj.
[00280] The transition time (Δt) corresponding to the collector voltage switching level is determined by the characteristics of the Push-pull amplifier together with the respective characteristics of the elements and circuit constants, as mentioned above, and is pre-stored as a constant in switching control unit 83 '.
[00281] Consequently, the gradients s1 to s16 corresponding to the collector voltage switching levels are also pre-stored constants. Operation of the Third Push-pull Amplifier: figures 5, 10 and 16
[00282] The characteristic part of the third Push-pull amplifier will be explained using figure 5, figure 10 and figure 16.
[00283] As in the explanation of the second Push-pull amplifier, voltages to be applied to the collector terminal of transistor NPN 17 or transistor PNP 18 in the push-pull amplifier 12 are given as Vc1 to Vc10.
[00284] Additionally, time points, at which the input signal waveform 131 becomes greater than Vth1 to Vth4, are given by t1 to t4, respectively, while leaving the time points at which it becomes smaller than Vth5-Vth8 being t9-t12, respectively.
[00285] An explanation will be given hereinafter for taking as an example a specific case in which the voltage level applied to the collector node of transistor NPN 17 changes from Vc1 to Vc2, for the sake of brevity.
[00286] First, a given time point contained in a time interval from a time point t1, in which an input signal becomes greater than the limit Vth1, for the delay time td, and a voltage level at this time, they are given as time point tn and voltage level Vn, respectively.
[00287] Still, a voltage that becomes a margin to prevent the NPN 17 transistor from reaching saturation is given by Vm. This Vm is set to a voltage value greater than the saturation voltage of the NPN 17 transistor.
[00288] And, the switching control unit 83 'calculates a time point ta (n) by Equation (3) below. ta (n) = (Vc1 - (Vc + Vm)) / s1 + tn. (Eq. 3)
[00289] Here, s1 is the gradient processed with linear approximation when the voltage applied to the collector terminal changes from Vc1 to Vc2.
[00290] Vm is the margin voltage to prevent transistor saturation, with respect to the voltage value Vn of a signal at the time point tn.
[00291] Briefly, in cases where a change in collector voltage is linearly approximated by a straight line with the gradient s1, time ta (n) is equivalent to an elevation delay (time point) of a signal switching control to supply the collector voltage that prevents transistor saturation with respect to a Vn signal at a given time tn. Calculation method of ta (n): figure 16
[00292] Here, a concrete explanation will be as a method of calculating the elevation timing of the switching control signal on the third push-pull amplifier.
[00293] A method for calculating ta (n) at a given time point tn within a period from time point t1 to t1 + td will be explained using figure 16. Figure 16 is an explanatory diagram showing how to obtain the elevation timing of the switching control signal C1 when the collector voltage is changed from Vc1 to Vc2.
[00294] To simplify the explanation, figure 16 shows a case to obtain ta (n) based on signals in data points T1, T2, T3 of this interval.
[00295] As previously mentioned, ta (n) is calculated by Equation (3). More specifically, as shown in figure 16, ta (n) at each of the time points T1, T2, T3 is obtained as a point at which a straight line with gradient s1 - this line passes through an addition point (Vn + Vm) of a margin voltage Vm to the voltage value V1, V2 or V3 at each time point - intercepts with the collector voltage Vc1.
[00296] In the example of figure 16, for time point T1, ta (1) is obtained as a crossing point of Vc1 and a line with gradient s1 passing through a point (V1 + Vm).
[00297] Similarly, for time point T2, ta (2) is obtained; for time point T3, ta (3) is obtained.
[00298] Then, the switching control unit 83 'of the third Push-pull amplifier specifies ta (2), which is the most preceding timing among ta (1) to ta (3), as a Vc1-to switching timing -Vc2 ta1.
[00299] By choosing the most preceding timing from the values of ta (n) calculated in this way, the voltage applied to the collector that is approximated by the gradient S1 does not go below the voltage of the signal Vn, thus allowing to prevent transistor saturation.
[00300] Similarly, for the change of each collector voltage level, the switching delay (ta2, ..., ta4, ta9, ..., ta12) at the moment of the switching control signal is obtained conform to the gradient. Note that ta2 to ta4 are the switching timings in the events for raising the switching control signals C2-C4; ta9-ta12 are the switching timings in the elevation events of the switching control signals C5-C8.
[00301] Note that in the switching control unit 83 'of the third Push-pull amplifier, the gradients s1-s4 and s9-s12 are pre-stored, which are in the case of changes that linearly approach the collector voltage in the respective elevation events of the respective switching control signals. Here, s1-s4 are gradients in the elevation events of the C1-C4 switching control signals, while s9-s12 are gradients in the elevation events of the C5-C8 switching control signals.
[00302] Gradients s1-s4 have positive polarity; gradients s9-s12 have negative polarity.
[00303] And, in the third Push-pull amplifier, the switching control unit 83 'compares the voltage of an input signal with the limit to determine a switching control signal to perform switching based on the level of such signal input and in the direction of a change, performs the aforementioned arithmetic processing in switching control signal elevation events. The switching control unit raises the switching control signal at a time earlier than the specific delay time td for a length of time equal to a difference between an over-limit timer and the switching timer ta1, ..., ta4, ta9, ..., ta12.
[00304] Basically, in the case of raising the switching control signal, the third push-pull amplifier subtracts from the delay time td in the timing control unit 121 a time difference between the switching timing (ta (n )) which has been calculated in accordance with the input signal and the collector voltage gradient transition at each level and the time point at which the input signal exceeds the limit, and uses the calculated time as the delay delay time of each switching control signal.
[00305] Alternatively, in switching control signal drop events, a delay delay time is used, which is adjusted with the specific delay time td.
[00306] In short, the third Push-pull amplifier increases the potential at a time earlier than the delayed signal in switching control signal raising events and, in switching control signal falling events, performs drop in a delay tuned to the delayed signal.
[00307] More specifically, the elevation delay time (level L ^ level H) and fall time (level H ^ level L) of the respective switching control signals on the third push-pull amplifier are given as follows: C1 Rising: td1 = td- (t1-ta1), C2 Rising: td2 = td- (t2-ta2), C3 Rising: td3 = td- (t3-ta3), C4 Rising: td4 = td- (t4-ta4), C4 Lowering: td5 = td, C3 Lowering: td6 = td, C2 Lowering: td7 = td, C1 Lowering: td8 = td, C5 Rising: td9 = td- (t9- ta9), C6 Rising: td10 = td- (t10-ta10), C7 Rising: td11 = td- (t11-ta11), C8 Rising: td12 = td- (t12-ta12), C8 Lowering : td13 = td, C7 Lowering: td14 = td, C6 Lowering: td15 = td, C5 Lowering: td16 = td.
[00308] With this, it is possible to raise the switching control signal at a earlier time than the output signal of the push-pull amplifier was delayed by td, preventing transistor saturation even in the presence of the transition time of the collector voltage, and allow the collector voltage to track any steep elevation of an output signal, thus allowing the improvement of the distortion characteristics in the output signal.
[00309] In addition, even when the collector voltage drops it becomes slower due to the presence of a transition time, a voltage that exceeds the ideal collector voltage waveform is obtained; thus, transistor saturation does not occur at all. Effects of the Third Mode
[00310] In the current supply circuit according to the third modality of this invention, the switching control unit 83 'is arranged to pre-store gradients in case of linear transition approximation at each collector voltage level, compare an input signal with the limit to determine the H / L level of each switching control signal based on a resulting ratio of magnitude and direction of change. Then, the current supply circuit calculates arithmetically, in switching control signal elevation events, the switching time ta (n) which is the most preceding temperature, while ensuring that the transistor is not saturated by a signal voltage when the collector voltage transitions with the stored gradient, and employs, as the switching control signal delay time (time delay time) a length of time obtained by subtracting a difference (t (n) -ta ( n)) between a time point t (n), at which the signal exceeds the limit, and the switching delay from a specific delay time (td). Therefore, it is advantageously possible to raise the switching control signal - in order to avoid transistor saturation by taking into account the collector voltage transition time - early in relation to the signal that was delayed by td at the control unit. timing 121, thus making it possible to improve the distortion characteristics of the output signal.
[00311] Another advantageous effect of the third power supply circuit is as follows: it determines the delay delay time by computing ta (n) based on a fed signal; thus, it is possible to allow the collector voltage to respond quickly to, and track, any steep elevation edges of the broadband signals, thereby improving the distortion characteristics.
[00312] Another effect of the third power supply circuit is situated on its ability to determine the optimal switching connection timing in accordance with the current input waveform signal, thus allowing for another improvement in efficiency.
[00313] Another additional effect is that there is no need for memory to pre-store the transition time and the delay delay time; thus, it is possible to reduce the capacity of such memory.
[00314] In addition, the third power supply circuit is specifically arranged so that, in switching control signal drop events, it performs, without calculating the transition time, the potential drop of the control signal switching in a delayed delay from the input signal delay to the delay time td, thus making it possible to simplify processing.
[00315] In addition, by using the third power supply circuit as the power supply circuit for any of the ET and EER power amplifiers shown in figure 12, it is possible to further improve the efficiency of a total of power amplifier. Fourth Mode
[00316] A power supply circuit (fourth power supply circuit) according to the fourth embodiment of the present invention will be described.
[00317] The fourth power supply circuit is one that determines by arithmetic computation the switching timing of the switching control signal in the switching control unit 83 'of a Push-pull amplifier (fourth Push-pull amplifier) 12 no only in elevation events, but also in fall events.
[00318] Although in the third power supply circuit, mentioned above, the potential drop is performed in a delay delayed by the delay time td in the event of the switching control signal drop to obtain a sufficient delay time and thus To prevent transistor saturation, the fourth power supply circuit is arranged to further reduce the delay time, thereby forcing a current supply voltage to track the output waveform of the Push-pull amplifier 12 as much as possible.
[00319] The fourth power supply circuit is similar in configuration to the second and third power supply circuits and is partially different from the third power supply circuit in the processing of switching control unit 83 '.
[00320] The processing in the switching control unit 83 'to compute the delay delay time (td (n)) and the switching delay time (ta (n)) in a switching control signal rise event is the same as that of the third Push-pull amplifier. Operation of the fourth push-pull amplifier: figure 17
[00321] A concrete explanation will be given of a method of calculating the timing in event of elevation of the switching control signal, which is a characteristic part of the fourth Push-pull amplifier. Figure 17 is an explanatory diagram showing how to obtain the drop timing of the switching control signal C1, in the case of switching the collector voltage from Vc2 to Vc1.
[00322] As in the explanation of the second and third Push-pull amplifiers, let Vc1 to Vc10 be applied voltages to the collector terminal of transistor NPN 17 or transistor PNP 18 in the amplifier Push-pull 12; let t1 to t4 be time points, at which an input signal waveform becomes larger than Vth1 to Vth4, respectively; let t5-t8 be time points, at which the signal becomes smaller than Vth4-Vth1, respectively; let t9-t12 be time points, at which the signal is less than Vth5-Vth8, respectively; and, let t13- t16 be time points, at which it is greater than Vth8-Vth5, respectively.
[00323] Additionally, the switching control unit 83 'of the fourth Push-pull amplifier stores, as the gradient corresponding to a switching level of the collector voltage, a drop gradient (s5-s8, s13-s16) in addition to the elevation gradient.
[00324] The drop gradient of the transistor NPN 17 has a negative sign and is equal to or greater than the gradient in case the collector voltage transitions to a lower level of a step.
[00325] The elevation gradient of the PNP 18 transistor has a negative sign.
[00326] For the sake of simplicity, an explanation will be given hereinafter by exemplifying a case, in which the voltage level applied to the collector node of transistor NPN 17 changes from Vc2 to Vc1.
[00327] The gradient, in the case of the linear approximation of the collector voltage transition in this period, is given as s5.
[00328] As shown in figure 17, first of all, a time point, at which the input signal becomes smaller than the Vth1 limit (that is, goes below the Vth1 limit), is given by t8.
[00329] A given time point involved in a period between a time point t8 and a time point earlier than the time point t8 by a delay time td (ie, t8-td) is given by tn ; a voltage level at this time is given as Vn.
[00330] Still, let Vm be a voltage that becomes the margin to avoid saturation of the NPN 17 transistor.
[00331] At a given time point tn in this period, the switching control unit 83 'performs the following calculation: ta (n) = (Vc2- (Vn + Vm)) / s5 + tn.
[00332] To simplify the explanation, figure 17 shows a case where the ta (n) drop timing of the switching control signal C1 is obtained based on a signal of a given time point T1, T2, T3 or T4 in this period.
[00333] As shown in figure 17, ta (n) at each of the time points T1, T2, T3, T4 is obtained as a point at which a straight line with the gradient s5, which passes through a point (Vn + Vm) adding a margin voltage Vm to a corresponding signal voltage value V1, V2, V3 or V4, in which each time point intercepts a collector voltage Vc2.
[00334] In the example of figure 17, for time point T1, ta (1) is obtained as an intersection of a line with gradient s5 - this passes through (V1 + Vm) - and Vc2. Similarly, for time point T2, ta (2) is obtained; for time point T3, ta (3) is obtained; for time point T4, ta (4) is obtained.
[00335] And, the switching control unit 83 'of the fourth Push-pull amplifier lets ta (4), which is the last delay between ta (1) to ta (4), be a Vc2-to- Vc1 ta8.
[00336] Briefly, when the switching delay obtained in this way is used to cause the switching control signal of interest to drop, the transistor is no longer saturated by a signal in this period, in the case of the collector voltage drop with a transition time, thus allowing the collector voltage to track the output signal waveform more successfully.
[00337] And, in the fourth Push-pull amplifier, the switching control unit 83 'compares a voltage input signal with its limit to determine a switching control signal for performing the switching based on a signal level of input and change direction, performs arithmetic processing in the switch control signal rise and fall events, and elevates the switch control signal at a time earlier than the specific delay time td by a length of time that corresponds to a difference between an over-limit timer and the switching time ta1, ..., ta12.
[00338] In short, the fourth Push-pull amplifier operates in switching control signal rise / fall events to subtract, from the delay time td in the timing control unit 121, a time difference between the timing switching time (ta (n)) that was calculated depending on the input signal and the gradient of the collector voltage transition at each level and a time point (t (n)) at which the input signal goes up or below the limit, and employs the time calculated as the delay time delay for each switch control signal.
[00339] As mentioned above, in switching control signal elevation events, let the earliest delay without transistor saturation be ta (n); in switching control signal drop events, let the last delay with no transistor saturation be ta (n). Consequently, the time difference (t (n) -ta (n)) is such that the value in the elevation events is greater than a time difference in the fall events.
[00340] More specifically, the values of the delay time delay of the respective rise (level L ^ level H) / fall (level H ^ level L) events of switching control signal in the fourth push-pull amplifier are as follows : C1 Rising: td1 = td- (t1-ta1), C2 Rising: td2 = td- (t2-ta2), C3 Rising: td3 = td- (t3-ta3), C4 Rising : td4 = td- (t4-ta4), C4 Lowering: td5 = td- (t5-ta5), C3 Lowering: td6 = td- (t6-ta6), C2 Lowering: td7 = td- (t7-ta7), C1 Lowering: td8 = td- (t8-ta8), C5 Rising: td9 = td- (t9-ta9), C6 Rising: td10 = td- (t10-ta10), C7 Rising: td11 = td- (t11-ta11), C8 Rising: td12 = td- (t12-ta12), C8 Lowering: td13 = td- (t13-ta13), C7 Lowering: td14 = td- (t14-ta14), C6 Lowering: td15 = td- (t15-ta15), C5 Lowering: td16 = td- (t16-ta16).
[00341] With this, in the fourth Push-pull amplifier, computation based on the current input signal is performed not only in potential rise events, but also in fall events, to perform a control signal drop operation in a more antecedent delay than the output signal retrieved with td from the Push-pull amplifier, while avoiding transistor saturation, thus forcing the collector voltage to track the fall of the output signal as well as its elevation, thus allowing the improving the distortion characteristics of the output signal. Fourth Mode Effects
[00342] In the current supply circuit according to the fourth embodiment of this invention, the switching control unit 83 'is arranged to pre-store gradients in the case of linear approximation of rise / fall transitions at the respective voltage levels collector, compare an input signal with the limit to determine the H / L level of each switching control signal based on its magnitude ratio and direction of change. The current supply circuit calculates, in switching control signal elevation events, the earliest timing that avoids transistor saturation caused by signal voltage, calculates, in switching control signal drop events, the last delay that avoids transistor saturation, caused by signal voltage; let the calculated delay be the switching delay ta (n). The current supply circuit employs, as the delay time (delay time delay) of the switching control signal, a length of time obtained by subtracting a difference (t (n) -ta (n)) between a time point t (n) at which the signal exceeds / falls below the limit and the switching delay from specific delay time (td). Therefore, it is advantageously possible to perform a switching control signal rise / fall with the optimum delay time by considering the collector voltage transition time for the signal that was delayed by td in the timing control unit 121, to allow as soon as the collector voltage tracks the output signal, while preventing transistor saturation, thus making it possible to improve the distortion characteristics of the output signal.
[00343] Especially in the fourth power supply circuit, the optimal switching control signal rise / fall timing is calculated by arithmetic processing based on the current input signal; this is possible to supply the collector voltage that quickly follows any steep rise and fall of the broadband signal, thus allowing the improvement of the distortion characteristics of the output signal, while simultaneously improving the energy conversion efficiency.
[00344] Briefly, in the fourth power supply circuit, it is possible to determine the optimum on / off timing in accordance with the current input signal waveform, thus making it possible to further improve efficiency.
[00345] In addition, by using the fourth power supply circuit as power supply circuits for the ET and EER power amplifiers shown in figure 12, it is possible to further improve the efficiency of the power amplifier as a whole . Case of Application to Another Push-Pull Amplifier: Figure 11
[00346] An example that applies a Push-pull amplifier with another configuration with the first to the fourth power supply circuits, as mentioned above will be explained using figure 11. Figure 11 is an explanatory diagram showing a configuration of another amplifier Push-pull used on the second power supply circuit.
[00347] As shown in figure 11, the configuration of another Push-pull amplifier is substantially the same as that of the second Push-pull amplifier shown in figure 7; however, the first is different from the last in the diode connection of the first power supply voltage supply circuit to supply the collector voltage to the NPN transistor 17 and the second power supply voltage supply circuit to supply the supply voltage. collector to PNP 18 transistor.
[00348] The other constituent parts are the same as those of the second Push-pull amplifier; the operations of the timing control unit 121 and the switching control unit 83 'are also the same.
[00349] The first power supply voltage circuit of another Push-pull amplifier has B1-B4 blocks, each consisting of a series combustion of DC voltage source and switch with a diode being connected in parallel to them . All of these blocks B1-B4 are not connected in series, but the cathodes of the respective diodes 71-74 are connected together to node 90, which is coupled to the "-" side (the negative side) of the DC voltage source 81 on the side of the NPN17 transistor.
[00350] Similarly, the second supply voltage circuit of another Push-pull amplifier is arranged so that diodes 75-78 of blocks B5-B8 are connected to node 91, which is coupled to the side "+ "(positive side) of the DC voltage source 82 on the PNP 18 transistor side.
[00351] By independently connecting the diode of each block to the collector terminal of the transistor NPN 17 or transistor PNP 18 in this way, it is determined that, even when some of the DC voltage sources 51-54 are selected, only one diode is connected . This means that only the direct voltage corresponding to a single diode is always subtracted. Thus, it is possible to stabilize the energy supplied to the transistor NPN 17 and the transistor PNP 18.
[00352] In other words, according to the configuration of another Push-pull amplifier, it is possible to reduce the number of diodes that let current flow. Consequently, when comparing the case in which the current must flow through a plurality of diodes, as in the configuration examples of modes 1 - 4, mentioned above, it is possible to suppress the potential drop that occurs otherwise due to the voltage diode, thus allowing another improvement in efficiency.
[00353] Note that the other Push-pull amplifier, mentioned above, is applicable not only to the second power supply circuit, but also to the third or fourth power supply circuit.
[00354] Also note that when a configuration without the timing control unit 121 is used, the resulting circuit operates in a similar manner to the first Push-pull amplifier; thus, it offers, in addition to the effects of the first Push-pull amplifier, an effect of forcing the diode's direct voltage to remain constant in any possible state, thus allowing the stabilization of the current supply. INDUSTRIAL APPLICABILITY
[00355] The present invention can be adapted for use in power supply circuits that are used in power amplifiers of operational transmitters to carry out radio communications by means of high frequency broadband signals and are capable of improving the efficiency of energy conversion. LIST OF REFERENCE NUMBERS
[00356] 1.8 ... Input terminal, 2 ... Divider, 3 ... Envelope wave detector, 4 ... Power supply circuit, 5 ... RF limiting amplifier, 6. .. Main amplifier, 7, 9, 10 ... Output terminal, 11 ... DC / DC converter, 12 ... Push-pull amplifier, 13 ... Switching element, 14, 20, 21 .. Diode, 15 ... Inductance, 16 ... Operational amplifier, 17 ... NPN Transistor, 18 ... PNP Transistor, 19, 22 ... Resistor, 23, 24, 51, 52, 53, 54, 55, 56, 57, 58, 81, 82 ... DC power supply, 25 ... Current detector, 26 ... Hysteresis comparator, 61, 62, 63, 64, 65, 66, 67, 68 ... Switch, 71, 72, 73, 74, 75, 76, 77, 78 ... Diode, 83, 83 '... Switching control unit, 101, 142 ... NPN Transistor Collector voltage , 102, 143 ... PNP Transistor Collector voltage, 103, 113, 141 ... Output signal, 111 ... Ideal waveform, 112 ... Current waveform, 121 ... Control unit time delay, 131 ... The input signal, 201 ... Font and voltage, 202 ... Smoothing circuit, 203 ... Switching circuit, 204 ... Transformer, 205, 206, 207, 208 ... Rectifying / smoothing circuit, 209 ... Error amplifier, 210 ... Photo coupler, 211 ... Control circuit, 212 ... Drive circuit.

权利要求:
Claims (6)
[0001]
1. Power supply circuit used for power amplification, comprising: a Push-pull amplifier unit (17, 18) to amplify an input signal by Push-pull amplification schemes; a variable power supply unit (51-58, 61-68, 71-78) for varying a voltage level of a power supply voltage to be supplied to said Push-pull amplifier unit, by selectively connecting sources power (51-58) for the Push-pull amplifier according to control signals (C1-C8); a control unit (83) to supply the control signals (C1-C8) respectively corresponding to the power sources (51-58) of the variable power supply unit (51-58, 61-68, 71-78) According to the input signal, each of the control signals selecting connection / disconnection from a corresponding source of the power sources to the Push-pull amplifier unit (17, 18) according to the input signal, thereby controlling a voltage level of the power supply voltage, the circuit being characterized by the fact that a timing adjustment unit (121) to delay the input signal fed to the push-pull amplifier unit; where the variable power supply unit (51-58, 61-68, 71-78) is configured to adjust a voltage level of the power supply voltage in stages according to a number of power sources (51- 58) to be connected in order to connect the power source corresponding to the control signal when the control signal (C1-C8) is at a high level and disconnect the power source corresponding to the control signal when the control signal is at a low level, in order to change the power supply voltage to a predetermined level over a predetermined transition time, so as to connect the power source corresponding to the control signal (C1-C8) when the control signal control rises from low to high, and changes the power supply voltage to a predetermined level, so as to disconnect the power source corresponding to the control signal when the control signal falls from high to low, and the unit of control (83) is configured to increase or decrease the control signal when the input signal reaches a limit value (Vth1-Vth8) to change the voltage level of the power supply voltage, so that, in a case of elevation of the control signal from low to high level, increase the control signal at an earlier time, for a time corresponding to the transition time, than a time delay that is delayed from the time limit that has reached the limit value (Vth1-Vth8 ) for the delay time (td) in the timing adjustment unit (121), and in the event of a drop in the control signal from high to low level, lower the control signal in a time delay that is delayed from the time delay that reached the limit value (Vth1-Vth8) for the delay time (td).
[0002]
2. Power supply circuit according to claim 1, characterized by the fact that the control unit stores, for each of the control signals, as a delay delay time (td - Δt) for lifting, a length of time obtained by subtracting a transition time (Δt) from the delay time (td) in the timing adjustment unit corresponding to switching the elevation voltage level of the control signal from low to high level, stores, for each of the control signals, such as a delay delay time for the drop, the delay time (td) in the timing adjustment unit corresponding to the switching of the drop voltage level of the control signal from the high level to the low level, and in the case of raising / lowering the control signal, raises / lowers the control signal by a time delay that is delayed from the time when the input signal reached the limit value (Vth1-Vth8) for the change ten level are of the power supply voltage, by the referred delay time for rise / fall, respectively.
[0003]
3. Power supply circuit according to claim 1, characterized in that the said control unit (83) stores a transition gradient (S1-S4, S9-S12) of voltage level of the supply voltage energy corresponding to switching the elevation of the control signal from low to high level, and calculates, in the case of elevating the control signal from low to high level, a time delay for raising the control signal based on a signal input signal and in said gradient in order to supply the power supply voltage not saturating the push-pull amplifier unit, thus causing the control signal to rise at the calculated timing.
[0004]
4. Power supply circuit according to claim 3, characterized in that said control unit (83) stores a transition gradient (S5-S8, S13-S16) of voltage level of the supply voltage energy corresponding to the switching of the control signal drop from high to low level, and calculates, in the event of a drop in the control signal from high level to low level, a delay to lower said control signal based on a input signal detected and in said gradient, in substitution to lower the control signal in the delayed time delay, in which the input signal reached the limit value by the delay time (td), in order to supply the voltage of supply of unsaturated energy to the push-pull amplifier unit, thus causing the control signal to fall within the said calculated timing.
[0005]
5. ET power amplifier characterized by the fact that it comprises: 6. envelope wave detector (3) to perform wave detection of a signal inserted in the power amplifier; The power supply circuit (4) defined in any one of claims 1 to 4, which inserts an output signal from the envelope wave detector (3) and includes a class D circuit provided in an output step of the unit Push-pull amplification (17, 18); and a main amplifier (6) for amplifying a signal inserted in the power amplifier; wherein the power supply circuit (4) supplies the main amplifier (6) with a power supply voltage adapted to an envelope detected by said envelope wave detector (3).
[0006]
6. EER type power amplifier characterized by the fact that it comprises: an envelope wave detector (3) to perform wave detection of a signal inserted in the power amplifier; the power supply circuit (4) defined in any one of claims 1 to 4, which inserts an output signal from the envelope wave detector (3) and includes a class D circuit provided in an output step of the control unit Push-pull amplification (17, 18); a main amplifier (6) for amplifying an inserted signal; and a limiting amplifier (5) to limit an input signal voltage inserted into the power amplifier and to supply it to the main amplifier (6), where the power supply circuit (4) supplies the main amplifier (6) with a power supply voltage adapted to an envelope detected by said envelope wave detector (3).

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法律状态:
2018-12-04| B06F| Objections, documents and/or translations needed after an examination request according art. 34 industrial property law|

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2019-10-29| B06U| Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure|

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2020-07-28| B06A| Notification to applicant to reply to the report for non-patentability or inadequacy of the application according art. 36 industrial patent law|

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2020-11-10| B09A| Decision: intention to grant|

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2020-12-29| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 19/11/2012, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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JP2011257502A|JP5822683B2|2011-11-25|2011-11-25|Power circuit|

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JP2011-257502|2011-11-25|

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PCT/JP2012/079962|WO2013077290A1|2011-11-25|2012-11-19|Power supply circuit|

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